1. Field of the Invention
The present invention relates to a backside illuminated imaging device that performs imaging by illuminating light from a back side of a semiconductor substrate to generate electric charges in the semiconductor substrate based on the light and reading out the electric charges from a front side of the semiconductor substrate.
2. Description of Related Art
An imaging portion of a general solid-state imaging device is configured by arranging a plurality of fine photoelectric conversion cells including photodiodes in one or two dimensions. Since a high-resolution image can be captured by arranging an increased number of photoelectric conversion cells in a device of a limited size, it is desired to miniaturize the photoelectric conversion cells. The miniaturization limit is determined by a wavelength of light of a detection target and is determined by a wavelength (400-700 nm) of a visible light region in the case of a general visible light image sensor.
In the case of a general (frontside illuminated type) image sensor, a photoelectric conversion portion of each cell is formed below a wiring layer in which an electrode or the like is arranged. A wiring portion of the wiring layer interferes with transmission of light incident into each photoelectric conversion portion. For this, various devices are provided. For example, when an area of each cell is about 2×2 (μm), an effective opening area of a light receiving portion is 1×1 (μm) in most cases. It has been found that sensitivity is abruptly degraded according to cell miniaturization in principle.
Accordingly, a backside illuminated imaging device has been considered. That is, a light receiving portion is provided in a backside opposite to a front side surface of a semiconductor substrate in which a wiring layer of an electrode or the like is formed. Signal charges based on light incident from the backside are generated in a photoelectric conversion portion of each cell. Since the opening area of the light receiving portion of each cell is not affected by the wiring layer, a relatively large opening area can be achieved and sensitivity degradation can be prevented even when the photoelectric conversion cell is miniaturized.
FIG. 38 is a schematic cross-sectional view of the most common structure of a CCD type solid-state imaging device of an interline type.
As shown in FIG. 38, a p-type semiconductor 102 including p-type impurities is formed in a deep portion of an n-type silicon substrate 101. In the surface portion of the n-type silicon substrate 101, an n-type semiconductor layer 104 including n-type impurities for accumulating electric charges and a p-type semiconductor layer 105 including high-concentration p-type impurities for preventing a surface dark current are formed. Electric charges generated in a region from the surface of the silicon substrate 101 to the surface of the p-type semiconductor 102 (i.e., a photoelectric conversion region for generating electric charges contributing to imaging) are accumulated in the n-type semiconductor layer 104. An element separation layer 103 for separating adjacent photoelectric conversion regions is formed in the silicon substrate 101.
A potential profile taken along the line A-A of FIG. 38 is shown in FIG. 39. A depletion layer thickness of the photoelectric conversion region is about 2 μm. The electric charges generated in the deep portion of the silicon substrate 101 are not transferred to the n-type semiconductor layer 104 and does not contribute to imaging. FIG. 40 shows the relationship between the depletion layer thickness of the photoelectric conversion region and the optical absorptance of the photoelectric conversion region. An optical absorption coefficient of silicon depends on a wavelength as shown in FIG. 41. As a light wavelength is long, the light is transmitted up to the deep portion of the silicon substrate 101.
For example, when green light of a wavelength of 550 nm is considered, only light of 75% is absorbed in the depletion layer thickness of 2 μm and light of 97% is absorbed in the depletion layer thickness of 5 μm. From properties as shown in FIG. 40, it can be seen that it is preferable to form the depletion layer thickness of 5 μm or more in the photoelectric conversion region in order to implement high sensitivity.
A backside illuminated imaging device performs imaging by illuminating light from a back side of a semiconductor substrate, accumulating electric charges generated in the semiconductor substrate based on the light, and externally outputting signals base based on the accumulated electric charges by means of a charge coupled device (CCD) or complementary metal oxide semiconductor (CMOS) circuit or the like. This device is a solid-state imaging device for illuminating and employing light from the back side of the silicon substrate 101 in FIG. 38.
It is well known that this backside illuminated imaging device can realize high photoelectric conversion efficiency. Accordingly, if the depletion layer thickness has 10 μm or more in the backside illuminated imaging device, a device having very high sensitivity can be realized. However, a continuous potential slope from the backside of the silicon substrate into which light is incident to a charge accumulation layer formed on the surface of the silicon substrate should be formed to surely realize a signal charge separation between different photoelectric conversion regions. In other words, electric charges generated in the vicinity of the silicon substrate backside of each photoelectric conversion region should be able to be accurately transferred to the charge accumulation layer within the photoelectric conversion region.
In a general embedded photodiode, a depletion voltage is 3-4 V. A potential difference is only 3-4 V when the potential of a p-type semiconductor layer for reducing a dark current provided in a silicon substrate backside of a backside illuminated imaging device is set to 0 V. It is very difficult to form a depletion layer having a thickness of 10 μm in the continuous potential slope.
There has been proposed a technique capable of forming a continuous potential slope by stacking a plurality of n-type semiconductor layers formed by gradually varying an impurity concentration of the silicon substrate 101 between the p-type semiconductor layer 102 and the n-type semiconductor layer 104 shown in FIG. 38 (see JP-A-2006-134915).
FIG. 42 is a view showing simulation results of a backside illuminated imaging device in a concentration profile as shown in an embodiment of JP-A-2006-134915. In FIG. 42, a coordinate axis z represents the depth of a semiconductor substrate, and z=0 represents the surface of the semiconductor substrate. From device simulations executed in a concentration profile as shown in the embodiment of JP-A-2006-134915, it can be seen that the concentration profile of the embodiment is not actual since an electron pool is formed in a large portion of a photoelectric conversion region. As shown in FIG. 43, a maximum potential point occurs in a position of 3 μm from the semiconductor substrate surface even when similar device simulations are executed by decreasing the number of digits representing the concentration of the concentration profile as shown in the embodiment of JP-A-2006-134915 by 2. When signal charges accumulated in this depth are read out from a CCD or CMOS formed in the semiconductor substrate surface, there is a difficulty since a problem of a residual image or the like occurs.
Also in the backside illuminated imaging device like the frontside illuminated type imaging device, an overflow drain structure should be provided to discharge unwanted electric charges, unnecessary for image pickup, accumulated in a photoelectric conversion element. Overflow drain structures applicable to the backside illuminated imaging device are a vertical type overflow drain structure and a horizontal type overflow drain structure. Since a drain region is arranged adjacent and parallel to each photoelectric conversion element in the horizontal type overflow drain structure, a size of each constituent element may not sufficiently increase when miniaturization is carried out in this structure, such that it is difficult to keep a saturation signal amount (or to improve the sensitivity). On the other hand, the vertical type overflow drain structure may secure a size of each constituent element even when miniaturization is carried out since the drain region is provided below each photoelectric conversion element, such that a saturation signal amount may be kept (the sensitivity may be improved).
JP-A-2001-257337 discloses a configuration adopting the vertical overflow drain structure in the backside illuminated imaging device.
JP-A-2006-49338 discloses a configuration in which an overflow drain structure is provided on a surface of a backside illuminated imaging device.
Since the configuration disclosed in JP-A-2001-257337 is that in which light illuminated from a backside of the backside illuminated imaging device is incident into a vertical overflow drain region and the light passed through the vertical overflow drain region is incident into a photoelectric conversion element, electric charges generated in the vertical overflow drain region and its depletion layer are discharged from the drain region. Since this drain region is present in a swallow position within a semiconductor substrate viewed from an incident light side, a lot of light of a wavelength band of the blue color is absorbed therein. As a result, the imaging device has a remarkable low blue sensitivity.
According to the configuration as disclosed in JP-A-2006-49338, the degradation of blue sensitivity may be prevented. However, since a drain region is not provided above a position separated from a maximum potential point of a photodiode, excessive charges may not be sufficiently discharged. Specifically, when an electronic shutter function is realized by discharging all electric charges accumulated in the photodiode, fixed pattern noise or the like is caused by electric charges residual in the photodiode when the electronic shutter is turned on.
Incidentally, a defect of a semiconductor device occurs due to contamination by heavy metal during a fabrication process, such that a device property may be deteriorated or reliability may be degraded. There is a gettering technique for reducing the effect of this metal contamination. Since an image sensor is very sensitive to noise occurring due to a dark current, sufficient light shielding is required, but the dark current is apt to increase also in contamination by heavy metal. Accordingly, when the image sensor is manufactured, the sufficient gettering property is required for a semiconductor device.
When a frontside illuminated type imaging device is manufactured, a manufacturing method based on “backside gettering” is conventionally adopted to provide the sufficient gettering effect to a backside of a semiconductor substrate using a defect-free thick epitaxial wafer or a wafer based on phosphorus gettering or polyback seal.
However, since the light receiving portion is to be provided in the backside of the semiconductor substrate when the backside illuminated imaging device is manufactured, the two sides (or the top and bottom) of the semiconductor substrate are conventionally reversed during a manufacturing process. Accordingly, when the frontside illuminated type imaging device is manufactured, “backside gettering” to be conventionally performed may not be applied, such that there is a high possibility that the required sufficient gettering property is not obtained.
In general, a silicon-on-insulator (SOI) substrate is used as a semiconductor wafer when a backside illuminated imaging device is manufactured. In this case, since a Si/SiO2 interface serving as an interface of an SOI layer and a BOX layer forming a semiconductor substrate functions as a robust gettering side, contaminated heavy metal may be protected. A backside of the substrate is thick (i.e., generally 600 μm) in the case of the backside illuminated imaging device, whereas an interface itself of the SOI layer and the BOX layer forming the semiconductor substrate is close to a device operation region (i.e., a depletion region). Accordingly, there is a high possibility that the gettering side becomes a dark current source, that is, a noise source.